Multiple logic blocks can be incorporated into a single integrated circuit, often on a single semiconductor die. In some designs, the topology of an on-chip fabric interconnect and various device positions may be predefined for a variety of reasons, including for bandwidth, floor plan, physical timing, and so on.
Introducing additional layers in a topology to incorporate root port or switch port modules can cause disruption in chip layout and resynthesizing the design for each product, increasing effort and turnaround time. Introducing additional stages in a fabric hierarchy also can impact latency/performance due to additional staging in transaction processing. In another scenario, there may be a desire to have different versions of an acceleration complex, one for on-chip integration and another for an off-chip form factor. Existing approaches cannot support this type of reuse of synthesized design sections, because of drastic changes in a given fabric hierarchy to support different variations.